The invention relates to a signal generating circuit and related method thereof, and more particularly, to a signal generating circuit for generating a validation signal and related method thereof.
In today's computer systems, because the processing speed of the CPU has improved, the transmission efficiency of each interface becomes a more important key point. As known by those skilled in the art, IDE interface was originally utilized in the computer system. However, in order to provide higher transmission efficiency, a new interface, the serial ATA (SATA) interface, is now disclosed. Utilizing the SATA interface is no doubt improving the data access efficiency such that a user doesn't have to spend so much time to store data in SATA devices (such as an SATA hard disk). In other words, the SATA interface may be a new generation of computer interface.
When the computer host must communicate with a SATA device, it is well known that the computer host and the SATA device must first establish the SATA channel. That is, the handshaking mechanism between the SATA device and the host has to be set up first. In order to establish the above-mentioned handshaking mechanism, please refer to FIG. 1 that shows a simplified diagram of a host 100 and a SATA device 110 according to the related art. As shown in FIG. 1, firstly, the host 100 sends a signal ComReset through the transmitter 101 of the host 100. The SATA device 110 receives the signal ComReset from the receiver 112 of the SATA device 110 and then detects whether the signal ComReset is correct. If the SATA device detects that the received signal is the signal ComReset, the SATA device 110 replies with a signal ComInit to the host through the transmitters 111 of the SATA device 110. Then, after receiving the signal ComInit through the receiver 102 of the host 100, the host 100 adjusts its inner resistance and replies with a signal ComWake to the SATA device 110. After receiving the signal ComWake, the SATA device 110 also adjusts its inner resistance and outputs the ComWake signal.
After the host 100 receives the ComWake signal, the host 100 and the SATA device 110 perform a series of operations (e.g., host 100 and SATA device 110 align operations and host 100 and SATA device 110 synchronization operations). Therefore, the SATA channel can be established such that the host 100 and the SATA device 110 can communicate with each other through a SATA interface.
Please refer to FIG. 2, which is a waveform diagram of OOB signals ComReset, ComInit, and ComWake according to the related art. As mentioned above, in order to establish the SATA channel(the handshaking mechanism), the host 100 and the SATA device 110 have to check the OOB signals and reply to each other by utilizing these signals. In fact, the SATA device 110 and the host 100 checks whether these OOB signals comply with specific waveforms in order to check whether the OOB signals are correct. Therefore, as shown in FIG. 2(a), the signals ComReset and ComInit have a specific waveform (pattern). That is, the signals ComReset and ComInit definitely have a plurality of bursts, where the width of each burst is 106.7 ns, and the time duration between every two successive bursts is 320 ns. Similarly, the signal ComWake, shown in the FIG. 2(b), also has a plurality of bursts, where the width of each burst is 106.7 ns, but the time duration between every two successive bursts is 106.7 ns. In general, these signals have a first state and a second state. The first state represents an idle state, and the second state represents a burst state. The time interval of the first state depends on different signals, as shown in FIG. 2. The burst contains four align primitives, and the align primitives are specific pattern, i.e. a plurality of pulses.
In implementation, the host 100 and the SATA device 110 utilizes a clock to count the burst and the time duration between two bursts in order to check the above-mentioned signals. Furthermore, the host 100 and the SATA device also utilize the clock to generate the response OOB signals, which comply with the above-mentioned patterns to each other such that the handshaking mechanism can be formed. Please note that the clock can be generated from a PLL circuit, which can utilize a crystal as its clock reference.
The determination circuit detects time period of first state and second state and recognizes the receiving signals is the COMRESET signal, the COMINIT signal, or the COMWAKE. Furthermore, the host 100 and the SATA device may utilize a clock to generate the response OOB signals, which comply with the above-mentioned waveform to each other such that the handshaking mechanism can be formed. Please note that the clock can be generated from a PLL circuit, which can utilize a crystal as its clock reference.
Unfortunately, the PLL circuit needs time to lock to a specific clock frequency. Therefore, when the PLL is in the process of locking to the specific clock frequency, but that the locking to the specific clock frequency has not yet been stabilized, the PLL generates incorrect clocks. In other words, when the output clock of the PLL circuit is not stabilized yet, the output clock cannot be utilized to generate OOB signals.
Please note that the incorrect clock can be divided into two different situations. That is, first, the frequency of the incorrect output clock may be too high (This means that the frequency of the incorrect output clock is over the acceptable working frequency range of the circuits of the SATA device.) Therefore, the unacceptable clock is impossible to be utilized. Second, the frequency of the incorrect output clock is in the acceptable working frequency range of the circuits of the SATA device, but not sufficient to generate correct OOB signals complying the specific waveform. In this situation, the circuits of the SATA device can utilize the acceptable clock to perform other tasks but generating the OOB signals.
However, in the above-mentioned two situations, the SATA device 110 cannot utilize the incorrect clocks to generate the OOB signals. Furthermore, if the SATA device 110 does utilize the incorrect clocks to generate the OOB signals, the host 100 may not recognize the COMINIT/COMWAKE.
In order to avoid the aforementioned problem, some related arts directly gate the output of the PLL circuit until the PLL circuit can generate the correct clock. This means that the PLL circuit ceases to output the incorrect output clock in the process of locking the reference clock. This can guarantee that no incorrect clock (including the acceptable clock and the high frequency clock) is outputted. In addition, other related arts show that the PLL circuit still sends out the incorrect clock to the SATA device 100 but the SATA device 110 will be reset before the PLL circuit generates the correct clock. Therefore, the SATA device 110 will properly utilize the correct clock without an error.
Apparently, the acceptable incorrect clocks can be utilized except generating the OOB signals, but the related art always ignore it. Therefore, according to the abovementioned related arts, some processing clock cycles (that is, the clock cycles of the acceptable clock) will be wasted for waiting for the generation of correct clock. For example, the acceptable incorrect clocks can be utilized to perform settings of transmit amplitude or to perform settings of SSC on/off.